As the semiconductor industry has progressed into nanometer technology process nodes in pursuit of higher device density, higher performance, and lower costs, challenges from both fabrication and design issues have resulted. In particular, increasing device density has produced very high gate heights and gate aspect ratio. High gate height and aspect ratio tends to lead to gate incline or collapse. In addition, as more steps are performed on semiconductor devices to increase device density, gate electrodes are exposed to an increasing number of process steps that can degrade the gate electrode and cause gate electrode height to shrink. If the gate height is too short the device can be damaged during the formation of overlying layers. A method of maintaining proper gate height throughout the semiconductor processing operations is desirable.